In recent years, with reductions in the sizes of semiconductor devices and increases in the numbers of wiring layers of the semiconductor devices, the flatness of each of layers has been demanded. Specifically, it is important that copper-plated surfaces of substrates be polished by chemical mechanical polishing (CMP) or the like and thereby uniformly planarized in a wiring process included in a process of manufacturing semiconductor devices in order to improve the qualities of the semiconductor devices.
The densities and edge lengths (lengths of circumferences of wirings) of the wirings of partial regions in a whole semiconductor device vary depending on wiring patterns within the partial regions. For example, if a plurality of wirings with smaller widths than the length of one side of a partial region are formed in the partial region, the edge lengths of the wirings tend to be larger than wirings included in other partial regions. On the other hand, if wirings with larger widths than the length of one side of a partial region are formed in the partial region, the edge lengths of the wirings tend to be smaller than wirings included in other partial regions. It is known that if the edge lengths of wirings of partial regions after wiring vary, an irregularity of a polished surface of a substrate increases, and the increase in the irregularity may degrade performance of a semiconductor device. Thus, attempts to set the densities and edge lengths of wirings of partial regions to values in certain ranges and reduce irregularities of polished surfaces of substrates have been conducted.
Japanese Laid-open Patent Publications Nos. 2009-111244 and 2004-88102 are examples of related art.
In order to suppress the densities and edge lengths of wirings of partial regions to values in certain ranges, the following method is considered. The method is to limit the maximum value of the densities of the wirings of the partial regions and the maximum value of the edge lengths of the wirings of the partial regions, insert a dummy wiring in a partial region in which the density of a wiring is low after a layout of the wirings, and thereby limit the minimum value of the densities of the wirings of the partial regions and the minimum value of the edge lengths of the wirings of the partial regions.
In this method, if the heights and widths of the wirings vary due to etching, either the densities of the wirings or the edge lengths of the wirings, or both densities of the wirings and edge lengths of the wirings, may not be in ranges from the minimum values to the maximum values.
An object of an aspect of the embodiments is to reduce variations, caused by etching, in the heights and widths of wirings.